1. Field of the Invention
The present invention relates to a trench isolation structure, a semiconductor device having this structure, and a trench isolation method, and more particularly, to a trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top corners of a trench and increasing the oxidation amount at these areas.
2. Description of the Related Art
Isolation between elements of a semiconductor device can be usually achieved by local oxidation of silicon (LOCOS) or trench isolation.
Between the two, the LOCOS method is simply conducted, and can simultaneously form wide isolation films and narrow isolation films. However, in the LOCOS method, a birds {character pullout}beak is formed by side oxidation, and thus an isolation region becomes wide, which leads to a reduction in the effective area of a source/drain region. Also, in the LOCOS method, stress which depends on the difference in a thermal expansion coefficient is concentrated at the edges of an oxide film during formation of a field oxide film, which causes crystal defects to be formed on a silicon substrate and results in a large amount of leakage current.
Hence, a trench isolation technique is necessarily required. Using a trench isolation technique, an isolation region can be kept small compared to the above-described LOCOS technique, with an effective isolation length made long at the same isolation width by forming a trench in a silicon substrate and filling the trench with a dielectric material such as oxide.
Among several processes for achieving isolation using trenches, how to form the profile of a trench is very important to produce a stable device. That is, a trench depth, a trench angle and the shape of a trench edge must be appropriately controlled. In particular, when shallow trench isolation (STI) is used in highly-integrated semiconductor devices, it is not too much to say that the electrical characteristics of devices are determined by the profile of the edge portions of a trench.
FIG. 1 is a cross-sectional view for explaining a problem which has been encountered in a conventional STI method. Here, reference numeral 1 is a semiconductor substrate, reference numeral 3 is an isolation film embedded in an STI region, reference numeral 5 is a gate oxide film, and reference numeral 7 is a gate electrode.
As shown in FIG. 1, the following problems occur when the edge portions of a trench are formed with a sharp angle of almost 90.degree.. First, a gate conductive layer covers the top corner portions of a trench during formation of a gate, so that an electric field is concentrated at the corners of a trench. As shown in FIG. 2, this leads to a hump phenomenon in which a transistor is turned on twice, and an inverse narrow width effect, resulting in degradation of the performance of transistors.
FIG. 3 is a graph showing an inverse narrow width effect occurring in an STI structure. As shown in this graph, an inverse narrow width effect represents a reduction in threshold voltage with a decrease in the channel width of a transistor. Here, reference character X represents data acquired before a hump phenomenon occurs, and reference character Y represents data acquired after a hump phenomenon occurs.
The second problem occurring when the edge portions of a trench are formed with a sharp angle of almost 90.degree. is degradation of the reliability of devices, such as, the dielectric breakdown of a gate oxide film caused by formation of a thin gate oxide film at the edge portions of a trench or by concentration of an electric field on the gate oxide film around the edges of a trench.
Several methods have been proposed to solve the above problems. One method is disclosed in U.S. Pat. Nos. 5,861,104 and 5,763,315.
U.S. Pat. No. 5,861,104 discloses a method of rounding the upper corners of a trench by improving a method of etching a trench. U.S. Pat. No. 5,763,315 discloses a method of rounding the upper edges of a trench by forming a (111) plane having a high oxidation rate on a semiconductor substrate with (100) crystal planes, using a wet etching technique or the like, and of preventing a degradation in the reliability of transistors and a gate oxide film by increasing the thickness of the gate oxide film which is formed on the upper edges of a trench.
The present invention intends to provide a structure for forming a (111) crystal plane on the upper edges of a trench to increase the thickness of a gate oxide film to be formed on these regions while rounding the upper edges of a trench, resulting in a significant improvement in the characteristics of transistors, and a fabrication method thereof.